As the semiconductor technology advances into deep submicron era, active areas of semiconductor devices, such as a MOS transistor, are generally isolated by STI structures. The method for fabricating the shallow trench isolation structure comprises: forming a shallow trench on a substrate by an etching process for isolating active areas within the substrate; filling up the shallow trench with a dielectric material to further cover the surface of the substrate; and planarizing the dielectric material to expose the surface of the substrate, wherein the planarization may be Chemical Mechanical Polishing (CMP). After formation of the STI, semiconductor devices, such as MOS transistors, are fabricated on the active areas between the STIs.
FIG. 1 shows STI structures formed by prior art, comprising: a semiconductor substrate 10; and STIs formed within the substrate, wherein the STIs are filled with dielectric materials 11, an active area is formed between the STIs within the substrate, and a semiconductor device (such as a MOS transistor comprising a gate structure, a source area and a drain area) is formed in the active area. However, in the prior art STIs, because of the planarization process and the cleaning process thereafter, downward depressions are formed between the surface of the dielectric material 11 and the surface of the adjacent substrate 10, which depressions are referred to divots 12. The divots 12 may lead to high leakage current and performance degradation of the semiconductor device. Moreover, with the scaling of the dimension of semiconductor devices, the dimension of the divots relative to the semiconductor device formed between the STIs becomes bigger, influences on performance of the semiconductor device become increasingly serious.